This invention relates to a sampling frequency converting device for converting the sampling frequency of input signals into an arbitrary sampling frequency by re-sampling, and a memory address control device for controlling the address used when reading out data from a memory unit.
Recently, digital audio signal reproducing devices for transmitting audio signals over an optical cable or a coaxial cable as digital signals and reproducing the digital audio signals via a digital audio interface have become popular. With such digital audio signal reproducing devices, a phase locked loop (PLL) made up of a phase comparator and a voltage controlled oscillator (VCO) is employed for generating clocks from received digital audio signals. However, with such digital audio signal reproducing device, digital/ analog (D/A) conversion characteristics tend to be lowered due to jitter introduced by the VCO in the PLL. Consequently, with a device for reproducing a digital audio signal recording medium, such as a compact disc (CD) player or a digital audio tape (DAT) player, there are occasions wherein satisfactory distortion-free audio signals may be produced by converting the digital audio signals into analog audio signals by D/A conversion using quartz clocks and the resulting analog audio signals are subsequently transmitted.
On the other hand, with a recording medium acting as a source for digital audio signals, such as CD, an optical disc smaller in size than CD, DAT or a digital audio tape smaller in size than DAT, the sampling frequency during recording of digital audio signals is not unified and may be any one of 44.1 kHz, 48 kHz or 32 kHz. With satellite broadcast (BS) which is not a recording medium but acts as a source for digital audio signals, the sampling frequency may be any one of the above-given sampling frequencies. Consequently, for recording the digital audio signals from DAT or BS with the sampling frequency of 44.1 kHz on a small-sized optical disc with the sampling frequency of 44.1 kHz, the digital audio signals from DAT or BS with the sampling frequency of 48 kHz need to be converted into analog signals by D/A conversion and subsequently re-converted into digital audio signals with the sampling frequency of 44.1 kHz by analog/digital (A/D) conversion, thus inevitably producing deterioration in characteristics due to distortion.
On the other hand, in mixing-recording digital audio signals using a DAT, respective digital audio signals to be mixed need to be converted into analog signals before proceeding to mixing if the different digital audio signals differ in the sampling frequency or in synchronization methods.
For preventing deterioration in playback digital audio signals due to-deterioration in performance due to clock jitter or difference in sampling frequencies for realizing free sampling frequency conversion, it has been desired to develop a non-synchronization type sampling frequency conversion device.
In general, such sampling frequency converting device exploits re-sampling time addresses for specifying re-sampling points for re-sampling a signal entered at a sampling frequency F.sub.si with a sampling frequency of F.sub.so. These re-sampling time addresses are generated in dependence upon the ratio of the sampling frequency of input signals (input sampling frequency) F.sub.si to the sampling frequency of re-sampled signals (output sampling frequency) F.sub.so.
In general, the present sampling frequency converting device employs the re-sampling time addresses for specifying the re-sampling points for re-sampling the input signal having the sampling frequency F.sub.si. The re-sampling time addresses are generated depending on the ratio of the sampling frequency of the input signal (input sampling frequency) F.sub.si and the sampling frequency of re-sampled signals (output sampling frequency) F.sub.so.
Specifically, the period t (=N.multidot.T.sub.so) equal to N times the period of the output sampling frequency F.sub.so (output sampling frequency) is counted with input reference clocks equal to M times the input sampling frequency F.sub.si (input master clocks) or MCK.sub.i (=M.multidot.F.sub.si) to find the sampling frequency ratio R between the input sampling frequency F.sub.si and the output sampling frequency F.sub.so, at the same time as jitter components such as F.sub.si, MCK.sub.i or F.sub.so are removed on averaging. The sampling frequency ratio R and the re-sampling time are cumulatively added together to generate the re-sampling time address. The re-sampling points stored in the re-sampling buffer memory are read out in accordance with the re-sampling time addresses for converting the sampling frequency.
Meanwhile, for such applications in which the input sampling frequency F.sub.si or the output sampling frequency F.sub.so are changed, there arises the inconvenience that an error tends to be transiently produced between the value of the sampling frequency ratio R and the actual ratio of F.sub.si /F.sub.so.
Consequently, high-precision conversion is realized under a condition of the constant input sampling frequency F.sub.si or the constant output sampling frequency F.sub.so.
In addition, if the sampling frequency ratio continues to be changed for a predetermined time, the re-sampling time address errors tend to accumulate under the effect of the temporal difference .DELTA.R of the sampling frequency ratio shown in FIG. 1, such that the buffer memory capacity is exceeded, thus leading to limitations imposed on the speed and amount of change of the sampling frequency ratio or to increased buffer memory capacity.
Alternatively, it may be felt that the re-sampling time address resolution may be improved by increasing the frequency of the input master clocks MCK.sub.i without the necessity of increasing the detection period t. However, in such case, the problem of limitations imposed on the operating speed of the circuit counters absorption and removal of input clock jitter. Thus it has not been possible to prevent errors from accumulating by simply increasing the frequency of the input master clocks MCK.sub.i for improving the re-sampling time address resolution, although the errors may thereby be reduced.
In addition, if, for performing frequency conversion with the above-described sampling frequency converting device, the power source is turned on, signal input/output is changed over, the noise is mixed or the input/output sampling frequency is rendered variable, the data write address for writing data in the re-sampling buffer memory or the data readout address for reading out data from the buffer memory approach or cross over each other, thus producing a non-continuous noise from the sampling frequency converting device.
For stabilizing the sampling frequency converting operation, it is necessary to initialize the memory readout addresses so that the absolute value of the difference between the write address and the readout address of the re-sampling buffer memory reaches its maximum value after stabilization of the operation of sampling frequency ratio detection for detecting the sampling frequency ratio. However, the initialization of the memory readout addresses is an operation difficult to achieve and signal interruption or noise tend to occur during the converting operation.